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Features
* Single 2.7V - 3.6V Supply * Dual-interface Architecture * * * * * * * * *
- Dedicated Serial Interface (SPI Modes 0 and 3 Compatible) - Dedicated Parallel I/O Interface (Optional Use) Page Program Operation - Single Cycle Reprogram (Erase and Program) - 8192 Pages (1056 Bytes/Page) Main Memory Supports Page and Block Erase Operations Two 1056-byte SRAM Data Buffers - Allows Receiving of Data while Reprogramming the Flash Array Continuous Read Capability through Entire Array - Ideal for Code Shadowing Applications Low-power Dissipation - 4 mA Active Read Current Typical - 2 A CMOS Standby Current Typical 20 MHz Maximum Clock Frequency - Serial Interface 5 MHz Maximum Clock Frequency - Parallel Interface Hardware Data Protection Commercial and Industrial Temperature Ranges
64-megabit 2.7-volt Only Dual-interface DataFlash(R) AT45DB642
Description
The AT45DB642 is a 2.7-volt only, dual-interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The dual-interface of the AT45DB642 allows a dedicated serial interface to be connected to a DSP and a dedicated parallel interface to be connected to a microcontroller or vice versa.
Pin Configurations
Pin Name CS SCK/CLK SI SO I/O7 - I/O0 WP RESET RDY/BUSY SER/PAR Function Chip Select Serial Clock/Clock Serial Input Serial Output Parallel Input/Output Hardware Page Write Protect Pin Chip Reset Ready/Busy Serial/Parallel Interface Control
Note:
NC NC RDY/BUSY RESET WP NC NC NC VCC GND NC NC NC NC CS SCK/CLK SI* SO* NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TSOP Top View Type 1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC NC NC NC NC I/O7* I/O6* I/O5* I/O4* VCCP* GNDP* I/O3* I/O2* I/O1* I/O0* SER/PAR* NC NC NC NC
DataFlash Card(1)
7654321
*Optional Use - See pin description text for connection information.
Note:
1. See AT45DCB008 Datasheet.
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However, the use of either interface is purely optional. Its 69,206,016 bits of memory are organized as 8192 pages of 1056 bytes each. In addition to the main memory, the AT45DB642 also contains two SRAM data buffers of 1056 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed, as well as reading or writing a continuous data stream. EEPROM emulation (bit or byte alterability) is easily handled with a selfcontained three step Read-Modify-Write operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash(R) uses either a serial interface or a parallel interface to sequentially access its data. The simple sequential access facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size and active pin count. DataFlash supports SPI mode 0 and mode 3. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage, and low-power are essential. The device operates at clock frequencies up to 20 MHz with a typical active read current consumption of 4 mA. To allow for simple in-system reprogrammability, the AT45DB642 does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB642 is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK), or a parallel interface consisting of the parallel input/output pins (I/O7 - I/O0) and the clock pin (CLK). The SCK and CLK pins are shared and provide the same clocking input to the DataFlash. All programming cycles are self-timed, and no separate erase cycle is required before programming. When the device is shipped from Atmel, the most significant page of the memory array may not be erased. In other words, the contents of the last page may not be filled with FFH.
Block Diagram
WP FLASH MEMORY ARRAY
PAGE (1056 BYTES)
BUFFER 1 (1056 BYTES)
BUFFER 2 (1056 BYTES)
SCK/CLK CS RESET VCC GND RDY/BUSY SER/PAR
I/O INTERFACE
SI
SO
I/O7 - I/O0
Memory Array
To provide optimal flexibility, the memory array of the AT45DB642 is divided into three levels of granularity comprising of sectors, blocks and pages. The "Memory Architecture Diagram" illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis; however, the optional erase operations can be performed at the block or page level.
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Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0 = 8 Pages 8448 bytes (8K + 256)
BLOCK ARCHITECTURE
SECTOR 0
BLOCK 0 BLOCK 1
PAGE ARCHITECTURE
8 Pages BLOCK 0
PAGE 0 PAGE 1
SECTOR 1 = 248 Pages 261,888 bytes (248K + 7936)
SECTOR 1
BLOCK 2
PAGE 6 PAGE 7 PAGE 8
BLOCK 30 SECTOR 2 = 256 Pages 270,336 bytes (256K + 8K) BLOCK 31
SECTOR 3 = 256 Pages 270,336 bytes (256K + 8K)
SECTOR 2
BLOCK 33
BLOCK 1
BLOCK 32
PAGE 9
PAGE 14 PAGE 15
BLOCK 62 BLOCK 63 BLOCK 64 SECTOR 31 = 256 Pages 270,336 bytes (256K + 8K) BLOCK 65
PAGE 16 PAGE 17 PAGE 18
SECTOR 32 = 256 Pages 270,336 bytes (256K + 8K)
PAGE 8189 BLOCK 1022 BLOCK 1023 PAGE 8190 PAGE 8191
Block = 8448 bytes (8K + 256)
Page = 1056 bytes (1K + 32)
Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Tables 1 through 4. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, toggling the SCK/CLK pin controls the loading of the opcode and the desired buffer or main memory address location through either the SI (serial input) pin or the parallel input pins (I/O7 - I/O0). All instructions, addresses, and data are transferred with the most significant bit (MSB) first. Buffer addressing is referenced in the datasheet using the terminology BFA10 - BFA0 to denote the 11 address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology PA12 - PA0 and BA10 - BA0, where PA12 PA0 denotes the 13 address bits required to designate a page address and BA10 - BA0 denotes the 11 address bits required to designate a byte address within the page.
Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data buffers. The DataFlash supports two categories of read modes in relation to the SCK/CLK signal. The differences between the modes are in respect to the inactive state of the SCK/CLK signal as well as which clock cycle data will begin to be output. The two categories, which are comprised of four modes total, are defined as Inactive Clock Polarity Low or Inactive Clock Polarity High and SPI Mode 0 or SPI Mode 3. A separate opcode (refer to Table 1 for a complete list) is used to select which category will be used for reading. Please refer to the "Detailed Bit-level Read Timing" diagrams in this datasheet for details on the clock cycle sequences for each mode.
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CONTINUOUS ARRAY READ: By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. To perform a continuous read, an opcode of 68H or E8H must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and a series of don't care bytes (four don't care bytes if using the serial interface or 60 don't care bytes if using the parallel interface). The first 13 bits (PA12 - PA0) of the 24-bit (three byte) address sequence specify which page of the main memory array to read, and the last 11 bits (BA10 BA0) of the 24-bit address sequence specify the starting byte address within the page. The four or 60 don't care bytes that follow the three address bytes are needed to initialize the read operation. Following the don't care bytes, additional clock pulses on the SCK/CLK pin will result in data being output on either the SO (serial output) pin or the parallel output pins (I/O7I/O0). The CS pin must remain low during the loading of the opcode, the address bytes, the don't care bytes, and the reading of data. When the end of a page in main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit (or byte if using the parallel interface mode) in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pins (SO or I/O7-I/O0). The maximum SCK/CLK frequency allowable for the Continuous Array Read is defined by the f CAR specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. BURST ARRAY READ WITH SYNCHRONOUS DELAY: The Burst Array Read with Synchronous Delay functions very similarly to the Continuous Array Read operation but allows much higher read throughputs by utilizing faster clock frequencies. It incorporates a synchronous delay (through the use of don't care clock cycles) when crossing over page boundaries. To perform a Burst Array Read with Synchronous Delay, an opcode of 69H or E9H must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and a series of don't care bytes (four don't care bytes if using the serial interface or 60 don't care bytes if using the parallel interface). The first 13 bits (PA12PA0) of the 24-bit (three byte) address sequence specify which page of the main memory array to read, and the last 11 bits (BA10-BA0) of the 24-bit address sequence specify the starting byte address within the page. The don't care bytes that follow the three address bytes are needed to initialize the read operation. Following the don't care bytes, additional clock pulses on the SCK/CLK pin will result in data being output on either the SO pin or the I/O7-I/O0 pins.
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As with the Continuous Array Read, the CS pin must remain low during the loading of the opcode, the address bytes, the don't care bytes, and the reading of data. During a Burst Array Read with Synchronous Delay, when the end of a page in main memory is reached (the last bit or the last byte of the page has been clocked out), the system must send an additional 32 don't care clock cycles before the first bit (or byte if using the parallel interface mode) of the next page can be read out. These 32 don't care clock cycles are necessary to allow the device enough time to cross over the burst read boundary (the crossover from the end of one page to the beginning of the next page). By utilizing the 32 don't care clock cycles, the system does not need to delay the SCK/CLK signal to the device which allows synchronous operation when reading multiple pages of the memory array. Please see the detailed read timing waveforms for illustrations (beginning on page 21) on which clock cycle data will actually begin to be output. When the last bit (or byte in the parallel interface mode) in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. The transition from the last bit (or byte when using the parallel interface) of the array back to the beginning of the array is also considered a burst read boundary. Therefore, the system must send 32 don't care clock cycles before the first bit (or byte if using the parallel interface mode) of the memory array can be read. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pins (SO or I/O7-I/O0). The maximum SCK/CLK frequency allowable for the Burst Array Read with Synchronous Delay is defined by the fBARSD specification. The Burst Array Read with Synchronous Delay bypasses both data buffers and leaves the contents of the buffers unchanged. MAIN MEMORY PAGE READ: A main memory page read allows the user to read data directly from any one of the 8192 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read, an opcode of 52H or D2H must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and a series of don't care bytes (four don't care bytes if using the serial interface or 60 don't care bytes if the using parallel interface). The first 13 bits (PA12 - PA0) of the 24-bit (three-byte) address sequence specify the page in main memory to be read, and the last 11 bits (BA10 - BA0) of the 24-bit address sequence specify the starting byte address within that page. The four or 60 don't care bytes that follow the three address bytes are sent to initialize the read operation. Following the don't care bytes, additional pulses on SCK/CLK result in data being output on either the SO (serial output) pin or the parallel output pins (I/O7 - I/O0). The CS pin must remain low during the loading of the opcode, the address bytes, the don't care bytes, and the reading of data. When the end of a page in main memory is reached, the device will continue reading back at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read operation and tristate the output pins (SO or I/O7 - I/O0). BUFFER READ: Data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. An opcode of 54H or D4H is used to read data from buffer 1, and an opcode of 56H or D6H is used to read data from buffer 2. To perform a buffer read, the opcode must be clocked into the device followed by three address bytes comprised of 13 don't care bits and 11 buffer address bits (BFA10 - BFA0). Following the three address bytes, an additional don't care byte must be clocked in to initialize the read operation. Since the buffer size is 1056 bytes, 11 buffer address bits are required to specify the first byte of data to be read from the buffer. The CS pin must remain low during the loading of the opcode, the address bytes, the don't care bytes, and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pins (SO or I/O7 - I/O0).
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STATUS REGISTER READ: The status register can be used to determine the device's ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or the device density. To read the status register, an opcode of 57H or D7H must be loaded into the device. After the opcode is clocked in, the 1-byte status register will be clocked out on the output pins (SO or I/O7 - I/O0), starting with the next clock cycle. When using the serial interface, the data in the status register, starting with the MSB (bit 7), will be clocked out on the SO pin during the next eight clock cycles. The five most-significant bits of the status register will contain device information, while the remaining three least-significant bits are reserved for future use and will have undefined values. After the one byte of the status register has been clocked out, the sequence will repeat itself (as long as CS remains low and SCK/CLK is being toggled). The data in the status register is constantly updated, so each repeating sequence will output new data. Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy state. The user can continuously poll bit 7 of the status register by stopping SCK/CLK at a low level once bit 7 has been output on the SO or I/O7 pin. The status of bit 7 will continue to be output on the SO or I/O7 pin, and once the device is no longer busy, the state of the SO or I/O7 pin will change from 0 to 1. There are eight operations that can cause the device to be in a busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program with Built-in Erase, Buffer to Main Memory Page Program without Built-in Erase, Page Erase, Block Erase, Main Memory Page Program, and Auto Page Rewrite. The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. The device density is indicated using bits 5, 4, 3 and 2 of the status register. For the AT45DB642, the four bits are logical "1"s. The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices, allowing a total of sixteen different density configurations.
Status Register Format
Bit 7 RDY/BUSY Bit 6 COMP Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 X Bit 0 X
Program and Erase Commands
BUFFER WRITE: Data can be clocked in from the input pins (SI or I/O7 - I/O0) into either buffer 1 or buffer 2. To load data into either buffer, a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by three address bytes comprised of 13 don't care bits and 11 buffer address bits (BFA10 - BFA0). The 11 buffer address bits specify the first byte in the buffer to be written. After the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. If the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer until a low-to-high transition is detected on the CS pin.
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BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written into either buffer 1 or buffer 2 can be programmed into the main memory. A 1-byte opcode, 83H for buffer 1 or 86H for buffer 2, must be clocked into the device followed by three address bytes consisting of 13 page address bits (PA12 - PA0) that specify the page in the main memory to be written and 11 don't care bits. When a low-to-high transition occurs on the CS pin, the part will first erase the selected page in main memory (the erased state is a logical 1) and then program the data stored in the buffer into the specified page in main memory. Both the erase and the programming of the page are internally self-timed and should take place in a maximum time of tEP. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy. BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A previouslyerased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. A 1-byte opcode, 88H for buffer 1 or 89H for buffer 2, must be clocked into the device followed by three address bytes consisting of 13 page address bits (PA12 - PA0) that specify the page in the main memory to be written and 11 don't care bits. When a low-to-high transition occurs on the CS pin, the part will program the data stored in the buffer into the specified page in the main memory. It is necessary that the page in main memory that is being programmed has been previously erased using one of the optional erase commands (Page Erase or Block Erase). The programming of the page is internally self-timed and should take place in a maximum time of tP. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy. Successive page programming operations, without doing a page erase, are not recommended. In other words, changing bytes within a page from a "1" to a "0" during multiple page programming operations without erasing that page is not recommended. PAGE ERASE: The optional Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to Main Memory Page Program without Built-in Erase command to be utilized at a later time. To perform a page erase, an opcode of 81H must be loaded into the device, followed by three address bytes comprised of 13 page address bits (PA12 - PA0) and 11 don't care bits. The 13 page address bits are used to specify which page of the memory array is to be erased. When a low-to-high transition occurs on the CS pin, the part will erase the selected page (the erased state is a logical 1). The erase operation is internally self-timed and should take place in a maximum time of tPE. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy. BLOCK ERASE: A block of eight pages can be erased at one time allowing the Buffer to Main Memory Page Program without Built-in Erase command to be utilized to reduce programming times when writing large amounts of data to the device. To perform a block erase, an opcode of 50H must be loaded into the device, followed by three address bytes comprised of 10 page address bits (PA12 -PA3) and 14 don't care bits. The 10 page address bits are used to specify which block of eight pages is to be erased. When a low-to-high transition occurs on the CS pin, the part will erase the selected block of eight pages. The erase operation is internally selftimed and should take place in a maximum time of tBE. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy.
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Block Erase Addressing
PA12 0 0 0 0 * * * 1 1 1 1 PA11 0 0 0 0 * * * 1 1 1 1 PA10 0 0 0 0 * * * 1 1 1 1 PA9 0 0 0 0 * * * 1 1 1 1 PA8 0 0 0 0 * * * 1 1 1 1 PA7 0 0 0 0 * * * 1 1 1 1 PA6 0 0 0 0 * * * 1 1 1 1 PA5 0 0 0 0 * * * 1 1 1 1 PA4 0 0 1 1 * * * 0 0 1 1 PA3 0 1 0 1 * * * 0 1 0 1 PA2 X X X X * * * X X X X PA1 X X X X * * * X X X X PA0 X X X X * * * X X X X Block 0 1 2 3 * * * 1020 1021 1022 1023
MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations. Data is first clocked into buffer 1 or buffer 2 from the input pins (SI or I/O7 - I/O0) and then programmed into a specified page in the main memory. A 1-byte opcode, 82H for buffer 1 or 85H for buffer 2, must first be clocked into the device, followed by three address bytes. The address bytes are comprised of 13 page address bits (PA12 - PA0) that select the page in the main memory where data is to be written, and 11 buffer address bits (BFA10 - BFA0) that select the first byte in the buffer to be written. After all address bytes are clocked in, the part will take data from the input pins and store it in the specified data buffer. If the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. When there is a low-to-high transition on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into that memory page. Both the erase and the programming of the page are internally self-timed and should take place in a maximum time of tEP. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy.
Additional Commands
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start the operation, a 1-byte opcode, 53H for buffer 1 and 55H for buffer 2, must be clocked into the device, followed by three address bytes comprised of 13 page address bits (PA12 - PA0), which specify the page in main memory that is to be transferred, and 11 don't care bits. The CS pin must be low while toggling the SCK/CLK pin to load the opcode and the address bytes from the input pins (SI or I/O7 - I/O0). The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the transfer of a page of data (tXFR), the status register can be read or the RDY/BUSY can be monitored to determine whether the transfer has been completed.
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MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can be compared to the data in buffer 1 or buffer 2. To initiate the operation, a 1-byte opcode, 60H for buffer 1 and 61H for buffer 2, must be clocked into the device, followed by three address bytes consisting of 13 page address bits (PA12 - PA0) that specify the page in the main memory that is to be compared to the buffer, and 11 don't care bits. The CS pin must be low while toggling the SCK/CLK pin to load the opcode and the address bytes from the input pins (SI or I/O7 I/O0). On the low-to-high transition of the CS pin, the 1056 bytes in the selected main memory page will be compared with the 1056 bytes in buffer 1 or buffer 2. During this time (tXFR), the status register and the RDY/BUSY pin will indicate that the part is busy. On completion of the compare operation, bit 6 of the status register is updated with the result of the compare. AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion. This mode is a combination of two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in Erase. A page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory. To start the rewrite operation, a 1-byte opcode, 58H for buffer 1 or 59H for buffer 2, must be clocked into the device, followed by three address bytes comprised of 13 page address bits (PA12 - PA0) that specify the page in main memory to be rewritten and 11 don't care bits. When a low-to-high transition occurs on the CS pin, the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page of main memory. The operation is internally self-timed and should take place in a maximum time of tEP. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy. If a sector is programmed or reprogrammed sequentially page by page, then the programming algorithm shown in Figure 1 (page 33) is recommended. Otherwise, if multiple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in Figure 2 (page 34) is recommended. Each page within a sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations in that sector.
Operation Mode Summary
The modes described can be separated into two groups - modes that make use of the Flash memory array (Group A) and modes that do not make use of the Flash memory array (Group B). Group A modes consist of: 1. Main Memory Page to Buffer 1 (or 2) Transfer 2. Main Memory Page to Buffer 1 (or 2) Compare 3. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase 4. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase 5. Page Erase 6. Block Erase 7. Main Memory Page Program through Buffer 8. Auto Page Rewrite 9. Group B modes consist of: 10. Buffer 1 (or 2) Read 11. Buffer 1 (or 2) Write 12. Status Register Read If a Group A mode is in progress (not fully completed), then another mode in Group A should not be started. However, during this time in which a Group A mode is in progress, modes in Group B can be started.
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This gives the DataFlash the ability to virtually accommodate a continuous data stream. While data is being programmed into main memory from buffer 1, data can be loaded into buffer 2 (or vice versa). See application note AN-4 ("Using Atmel's Serial DataFlash") for more details.
Pin Descriptions
SERIAL/PARALLEL INTERFACE CONTROL (SER/PAR): The DataFlash may be configured to utilize either its serial port or parallel port through the use of the serial/parallel control pin (SER/PAR). The Dual Interface offers more flexibility in a system design with both the serial and parallel modes offered on the same device. When the SER/PAR pin is held high, the serial port (SI and SO) of the DataFlash will be used for all data transfers, and the parallel port (I/O7 - I/O0) will be in a high impedance state. Any data presented on the parallel port while SER/PAR is held high will be ignored. When the SER/PAR is held low, the parallel port will be used for all data transfers, and the SO pin of the serial port will be in a high impedance state. While SER/PAR is low, any data presented on the SI pin will be ignored. Switching between the serial port and parallel port can be done at anytime provided the following conditions are met: 1) CS should be held high during the switching between the two modes. 2) T SPH (SER/PAR hold time) and TSPS (SER/PAR Setup time) requirements should be followed. Having both a serial port and a parallel port on the DataFlash allows the device to reside on two buses that can be connected to different processors. The advantage of switching between the serial and parallel port is that while an internally self-timed operation such as an erase or program operation is started with either port, a simultaneous operation such as a buffer read or buffer write can be started utilizing the other port. The SER/PAR pin is internally pulled high; therefore, if the parallel port is never to be used, then connection of the SER/PAR pin is not necessary. In addition, if the SER/PAR pin is not connected or if the SER/PAR pin is always driven high externally, then the parallel input/output pins (I/O7-I/O0), the VCCP pin, and the GNDP pin should be treated as "don't connects." SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data serially into the device. The SI pin is used for all data input, including opcodes and address sequences. If the SER/PAR pin is always driven low, then the SI pin should be a "don't connect". SERIAL OUTPUT (SO): The SO pin is an output-only pin and is used to shift data serially out from the device. If the SER/PAR pin is always driven low, then the SO pin should be a "don't connect". PARALLEL INPUT/OUTPUT (I/O7-I/O0): The I/O7-I/O0 pins are bidirectional and used to clock data into and out of the device. The I/O7-I/O0 pins are used for all data input, including opcodes and address sequences. The use of these pins is optional, and the pins should be treated as "don't connects" if the SER/PAR pin is not connected or if the SER/PAR pin is always driven high externally. SERIAL CLOCK/CLOCK (SCK/CLK): The SCK/CLK pin is an input-only pin and is used to control the flow of data to and from the DataFlash. Data is always clocked into the device on the rising edge of SCK/CLK and clocked out of the device on the falling edge of SCK/CLK. CHIP SELECT (CS): The DataFlash is selected when the CS pin is low. When the device is not selected, data will not be accepted on the input pins (SI or I/O7-I/O0), and the output pins (SO or I/O7-I/O0) will remain in a high impedance state. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition on the CS pin is required to end an operation. HARDWARE PAGE WRITE PROTECT: If the WP pin is held low, the first 256 pages (sectors 0 and 1) of the main memory cannot be reprogrammed. The only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously mentioned. The WP pin is internally pulled high; therefore, in low pin count applications, connection of the WP pin is not necessary if this pin and feature will not be utilized. However, it is recommended that the WP pin be driven high externally whenever possible.
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RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level. The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. The RESET pin is also internally pulled high; therefore, in low pin count applications, connection of the RESET pin is not necessary if this pin and feature will not be utilized. However, it is recommended that the RESET pin be driven high externally whenever possible. READY/BUSY: This open drain output pin will be driven low when the device is busy in an internally self-timed operation. This pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during programming/erase operations, compare operations, and page-to-buffer transfers. The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. PARALLEL PORT SUPPLY VOLTAGE (VCCP AND GNDP): The VCCP and GNDP pins are used to supply power for the parallel input/output pins (I/O7-I/O0). The VCCP and GNDP pins need to be used if the parallel port is to be utilized; however, these pins should be treated as "don't connects" if the SER/PAR pin is not connected or if the SER/PAR pin is always driven high externally.
Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI Mode 3 or Inactive Clock Polarity High. In addition, the output pins (SO or I/O7 - I/O0) will be in a high impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The SPI mode or the clock polarity mode will be automatically selected on every falling edge of CS by sampling the inactive Clock State. The SPI interface is controlled by the serial clock SCK, serial input SI and chip select CS pins. The sequential 8-bit parallel interface is controlled by the clock CLK, 8 I/Os and chip select CS pins. These signals must rise and fall monotonically and be free from noise. Excessive noise or ringing on these pins can be misinterpreted as multiple edges and cause improper operation of the device. The PC board traces must be kept to a minimum distance or appropriately terminated to ensure proper operation. If necessary, decoupling capacitors can be added on these pins to provide filtering against noise glitches. As system complexity continues to increase, voltage regulation is becoming more important. A key element of any voltage regulation scheme is its current sourcing capability. Like all Flash memories, the peak current for DataFlash occur during the programming and erase operation. The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during programming or erase can lead to improper operation and possible data corruption.
System Considerations
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1638F-DFLSH-09/02
Table 1. Read Commands
Command Continuous Array Read SPI Mode 0 or 3 Inactive Clock Polarity Low or High Burst Array Read with Synchronous Delay SPI Mode 0 or 3 Inactive Clock Polarity Low or High Main Memory Page Read SPI Mode 0 or 3 Inactive Clock Polarity Low or High Buffer 1 Read SPI Mode 0 or 3 Inactive Clock Polarity Low or High Buffer 2 Read SPI Mode 0 or 3 Inactive Clock Polarity Low or High Status Register Read SPI Mode 0 or 3 D7H D6H 57H D4H 56H D2H 54H E9H 52H E8H 69H SCK/CLK Mode Inactive Clock Polarity Low or High Opcode 68H
Table 2. Program and Erase Commands
Command Buffer 1 Write Buffer 2 Write Buffer 1 to Main Memory Page Program with Built-in Erase Buffer 2 to Main Memory Page Program with Built-in Erase Buffer 1 to Main Memory Page Program without Built-in Erase Buffer 2 to Main Memory Page Program without Built-in Erase Page Erase Block Erase Main Memory Page Program Through Buffer 1 Main Memory Page Program Through Buffer 2 SCK/CLK Mode Any Any Any Any Any Any Any Any Any Any Opcode 84H 87H 83H 86H 88H 89H 81H 50H 82H 85H
Table 3. Additional Commands
Command Main Memory Page to Buffer 1 Transfer Main Memory Page to Buffer 2 Transfer Main Memory Page to Buffer 1 Compare Main Memory Page to Buffer 2 Compare Auto Page Rewrite Through Buffer 1 Auto Page Rewrite Through Buffer 2 Note: SCK/CLK Mode Any Any Any Any Any Any Opcode 53H 55H 60H 61H 58H 59H
In Tables 2 and 3, an SCK/CLK mode designation of "Any" denotes any one of the four modes of operation (Inactive Clock Polarity Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3).
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Table 4. Detailed Bit-level Addressing Sequence
Address Byte Address Byte Address Byte Additional Don't Care Bytes Required N/A 4 or 60 Bytes* N/A 1 Byte N/A 1 Byte N/A x x x x B B x B x B B x B x x B B B x x x x B B x B x B B x B x x B B B x x x x B B x B x B B x B x x B B B N/A N/A N/A N/A 4 or 60 Bytes* 4 or 60 Bytes* N/A N/A N/A N/A N/A N/A N/A N/A N/A 4 or 60 Bytes* 1 Byte 1 Byte N/A B B B B B B 4 or 60 Bytes* 4 or 60 Bytes*
BA10
PA12
PA11
PA10
BA9
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1 x B x B x B
Opcode 50H 52H 53H 54H 55H 56H 57H 58H 59H 60H 61H 68H 69H 81H 82H 83H 84H 85H 86H 87H 88H 89H D2H D4H D6H D7H E8H E9H
Opcode
01010000P 01010010P 01010011P 01010100x 01010101P 01010110x 01010111 01011000P 01011001P 01100000P 01100001P 01101000P 01101001P 10000001P 10000010P 10000011P 10000100x 10000101P 10000110P 10000111x 10001000P 10001001P 11010010P 11010100x 11010110x 11010111 11101000P 11101001P
P P P x P x
P P P x P x
P P P x P x
P P P x P x
P P P x P x
P P P x P x
P P P x P x
P P P x P x
P P P x P x
x P P x P x
x P P x P x
x P P x P x
x B x B x B
x B x B x B
x B x B x B
x B x B x B
x B x B x B
x B x B x B
x B x B x B
x B x B x B
x B x B x B
x B x B x B
N/A
P P P P P P P P P x P P x P P P x x P P P P P P P P P x P P x P P P x x P P P P P P P P P x P P x P P P x x P P P P P P P P P x P P x P P P x x N/A P P P P P P P P P P P P P P P P P P P P P P P P P P P P P x P P x P P P x x P P P P P P P P P x P P x P P P x x P P P P P P P P P x P P x P P P x x P P P P P P P P P x P P x P P P x x P P P P P P P P P x P P x P P P x x P P P P P P P P P x P P x P P P x x
N/A
P P P P P P P P P x P P x P P P x x P P P P P P P P P x P P x P P P x x N/A P P P P B B B B B B B B B B B B x x x x B B x B x B B x B x x B B B x x x x B B x B x B B x B x x B B B x x x x B B x B x B B x B x x B B B x x x x B B x B x B B x B x x B B B x x x x B B x B x B B x B x x B B B x x x x B B x B x B B x B x x B B B x x x x
N/A
x x x x B B x B x B B x B x x B B B N/A B B B B
B B x B x B B x B x x B B B
Note:
P = Page Address Bit B = Byte/Buffer Address Bit x = Don't Care * 4 Bytes for Serial Interface 60 Bytes for Parallel Interface
BA0
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
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1638F-DFLSH-09/02
Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC and AC Operating Range
AT45DB642 Com. Operating Temperature (Case) Ind. VCC Power Supply Note:
(1)
0C to 70C -40C to 85C 2.7V to 3.6V
1. After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before an operational mode is started.
DC Characteristics
Symbol ISB ICC1(1) ICC2(2) ICC3 ICC4 ICC5 ICC6 ILI ILO VIL VIH VOL VOH Notes: Parameter Standby Current Active Current, Read Operation, Serial Interface Active Current, Read Operation, Parallel Interface Active Current, Program Operation, Page Program Active Current, Program Operation, Fast Page Program Active Current, Erase Operation, Page Active Current, Erase Operation, Block Input Load Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA; VCC = 2.7V IOH = -100 A VCC - 0.2V 2.0 0.4 Condition CS, RESET, WP = VIH, all inputs at CMOS levels f = 20 MHz; IOUT = 0 mA; VCC = 3.6V f = 5 MHz; IOUT = 0 mA; VCC = 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VIN = CMOS levels VI/O = CMOS levels Min Typ 2 4 8 20 30 20 20 Max 10 10 15 35 50 35 35 1 1 0.6 Units A mA mA mA mA mA mA A A V V V V
1. ICC1 during a buffer read is 20 mA maximum. 2. ICC2 during a buffer read is 25 mA maximum.
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AC Characteristics - Serial/Parallel Interface
Symbol tSPH tSPS Parameter SER/PAR Hold Time SER/PAR Setup Time Min 100 100 Max Units ns ns
AC Characteristics - Serial Interface
Symbol fSCK fCAR fBARSD tWH tWL tCS tCSS tCSH tCSB tSU tH tHO tDIS tV tXFR tEP tP tPE tBE tRST tREC Parameter SCK Frequency SCK Frequency for Continuous Array Read SCK Frequency for Burst Array Read with Synchronous Delay SCK High Time SCK Low Time Minimum CS High Time CS Setup Time CS Hold Time CS High to RDY/BUSY Low Data In Setup Time Data In Hold Time Output Hold Time Output Disable Time Output Valid Page to Buffer Transfer/Compare Time Page Erase and Programming Time Page Programming Time Page Erase Time Block Erase Time RESET Pulse Width RESET Recovery Time 10 1 5 10 0 18 20 700 20 14 8 12 22 22 250 250 250 150 Min Max 20 15 20 Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns s ms ms ms ms s s
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1638F-DFLSH-09/02
AC Characteristics - Parallel Interface
Symbol fSCK1 fCAR1 fBARSD1 tWH tWL tCS tCSS tCSH tCSB tSU tH tHO tDIS tV tXFR tEP tP tPE tBE tRST tREC Parameter CLK Frequency CLK Frequency for Continuous Array Read CLK Frequency for Burst Array Read with Synchronous Delay CLK High Time CLK Low Time Minimum CS High Time CS Setup Time CS Hold Time CS High to RDY/BUSY Low Data In Setup Time Data In Hold Time Output Hold Time Output Disable Time Output Valid Page to Buffer Transfer/Compare Time Page Erase and Programming Time Page Programming Time Page Erase Time Block Erase Time RESET Pulse Width RESET Recovery Time 10 1 75 25 0 55 70 700 20 14 8 12 80 80 250 250 250 150 Min Max 5 3 5 Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns s ms ms ms ms s s
Test Waveforms and Measurement Levels
AC DRIVING LEVELS 2.4V 2.0 0.8 0.45V AC MEASUREMENT LEVEL
tR, tF < 3 ns (10% to 90%)
Output Test Load
DEVICE UNDER TEST 30 pF
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AC Waveforms
Two different timing diagrams are shown below. Waveform 1 shows the SCK/CLK signal being low when CS makes a high-to-low transition, and Waveform 2 shows the SCK/CLK signal being high when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup and hold times for the input signals (SI or I/O7-I/O0) are referenced to the low-to-high transition on the SCK/CLK signal. Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows timing that is compatible with SPI Mode 3.
Waveform 1 - Inactive Clock Polarity Low and SPI Mode 0
tCS CS tCSS SCK/CLK tV SO or I/O7 - I/O0 (OUTPUT) SI or I/O7 - I/O0 (INPUT) HIGH IMPEDANCE tSU VALID IN tH tHO VALID OUT tDIS HIGH IMPEDANCE tWH tWL tCSH
Waveform 2 - Inactive Clock Polarity High and SPI Mode 3
tCS CS tCSS SCK/CLK tV SO or I/O7 - I/O0 (OUTPUT) SI or I/O7 - I/O0 (INPUT) HIGH Z tSU VALID IN tHO VALID OUT tH tDIS HIGH IMPEDANCE tWL tWH tCSH
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1638F-DFLSH-09/02
Reset Timing (Inactive Clock Polarity Low Shown)
CS
tREC tCSS
SCK/CLK
tRST
RESET HIGH IMPEDANCE SO or I/O7 - I/O0 (OUTPUT) SI or I/O7 - I/O0 (INPUT) HIGH IMPEDANCE
Note:
The CS signal should be in the high state before the RESET signal is deasserted.
Serial/Parallel Interface Timing
CS
SER/PAR
tSPH tSPS
Command Sequence for Read/Write Operations (Except Status Register Read)
SI or I/O7 - I/O0 (INPUT) CMD 8 bits 8 bits 8 bits
MSB
XXXX XXXX
XXXX XXXX
XXXX XXXX
LSB
Page Address (PA12 - PA0)
Byte/Buffer Address (BA10 - BA0/BFA10 - BFA0)
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Write Operations
The following block diagram and waveforms illustrate the various write sequences available.
FLASH MEMORY ARRAY
PAGE (1056 BYTES)
BUFFER 1 TO MAIN MEMORY PAGE PROGRAM MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 2 BUFFER 2 TO MAIN MEMORY PAGE PROGRAM
BUFFER 1 (1056 BYTES)
BUFFER 1 WRITE MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 1
BUFFER 2 (1056 BYTES)
BUFFER 2 WRITE
I/O INTERFACE
SI
I/O7 - I/O0
Main Memory Page Program through Buffers
* Completes writing into selected buffer * Starts self-timed erase/program operation
CS SI or I/O7 - I/O0 (INPUT)
CMD PA12-5 PA4-0, BFA10-8 BFA7-0 n n+1 Last Byte
Buffer Write
* Completes writing into selected buffer
CS SI or I/O7 - I/O0 (INPUT)
CMD X X***X, BFA10-8 BFA7-0 n n+1 Last Byte
Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)
Starts self-timed erase/program operation
CS SI or I/O7 - I/O0 (INPUT)
CMD PA12-5
PA4-0, XXX
X***X
Each transition represents 8 bits
n = 1st byte read n+1 = 2nd byte read
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1638F-DFLSH-09/02
Read Operations
The following block diagram and waveforms illustrate the various read sequences available.
FLASH MEMORY ARRAY
PAGE (1056 BYTES)
MAIN MEMORY PAGE TO BUFFER 1 MAIN MEMORY PAGE TO BUFFER 2
BUFFER 1 (1056 BYTES)
BUFFER 1 READ
BUFFER 2 (1056 BYTES)
MAIN MEMORY PAGE READ BUFFER 2 READ
I/O INTERFACE
SO
I/O7 - I/O0
Main Memory Page Read
CS SI or I/O7 - I/O0 (INPUT) SO or I/O7 - I/O0 (OUTPUT)
CMD PA12-5 PA4-0, BA10-8 BA7-0 X X n n+1
Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Starts reading page data into buffer
CS SI or I/O7 - I/O0 (INPUT) SO or I/O7 - I/O0 (OUTPUT)
CMD PA12-5 PA4-0, XXX X
Buffer Read
CS SI or I/O7 - I/O0 (INPUT) SO or I/O7 - I/O0 (OUTPUT)
CMD X BFA10-8 BFA7-0 X n n+1
Each transition represents 8 bits
n = 1st byte read n+1 = 2nd byte read
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Detailed Bit-level Read Timing - Inactive Clock Polarity Low
Continuous Array Read (Opcode: 68H)
CS
SCK tSU SI
1
2
63
64
65
66
67
68
0
1
X
X
tV SO HIGH IMPEDANCE
DATA OUT
D7 D6 D5 D2 D1
LSB D0
MSB D7 D6 D5
BIT 8447 OF PAGE n
BIT 0 OF PAGE n+1
Burst Array Read with Synchronous Delay (Opcode: 69H)
CS
SCK tSU SI
1
2
63
64
65
66
67
1
2
31
32
33
32 CLOCKS
0 1 X X
tV SO HIGH IMPEDANCE
D7
DATA OUT
D6 D1
LSB D0 Don't Care
MSB D7 D6
BIT 8447 OF PAGE n
BIT 0 OF PAGE n+1
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1638F-DFLSH-09/02
Detailed Bit-level Read Timing - Inactive Clock Polarity Low (Continued)
Main Memory Page Read (Opcode: 52H)
CS
SCK tSU
1
2
3
4
5
60
61
62
63
64
65
66
67
COMMAND OPCODE SI
0 1 0 1 0 X X X X X
tV SO HIGH IMPEDANCE
DATA OUT
D7 MSB D6 D5
Buffer Read (Opcode: 54H or 56H)
CS
SCK tSU
1
2
3
4
5
36
37
38
39
40
41
42
43
COMMAND OPCODE SI
0 1 0 1 0 X X X X X
tV SO HIGH IMPEDANCE
DATA OUT
D7 MSB D6 D5
Status Register Read (Opcode: 57H)
CS
SCK tSU
1
2
3
4
5
6
7
8
9
10
11
12
16
17
COMMAND OPCODE SI
0 1 0 1 0 1 1 1
tV SO HIGH IMPEDANCE
D7 MSB
STATUS REGISTER OUTPUT
D6 D5 D1 D0 LSB D7 MSB
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Detailed Bit-level Read Timing - Inactive Clock Polarity High
Continuous Array Read (Opcode: 68H)
CS
SCK tSU SI
1
2
63
64
65
66
67
0
1
X
X
X
tV SO HIGH IMPEDANCE
DATA OUT
D7 D6 D5 D2 D1
LSB D0
MSB D7 D6 D5
BIT 8447 OF PAGE n
BIT 0 OF PAGE n+1
Burst Array Read with Synchronous Delay (Opcode: 69H)
CS
SCK tSU SI
1
2
63
64
65
66
1
2
31
32
33
32 CLOCKS
0 1 X X X
tV SO HIGH IMPEDANCE
D7
DATA OUT
D6 D1
LSB D0 Don't Care
MSB D7 D6
BIT 8447 OF PAGE n
BIT 0 OF PAGE n+1
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1638F-DFLSH-09/02
Detailed Bit-level Read Timing - Inactive Clock Polarity High (Continued)
Main Memory Page Read (Opcode: 52H)
CS
SCK tSU
1
2
3
4
5
61
62
63
64
65
66
67
68
COMMAND OPCODE SI
0 1 0 1 0 X X X X X
tV SO HIGH IMPEDANCE
D7 MSB
DATA OUT
D6 D5 D4
Buffer Read (Opcode: 54H or 56H)
CS
SCK tSU
1
2
3
4
5
37
38
39
40
41
42
43
44
COMMAND OPCODE SI
0 1 0 1 0 X X X X X
tV SO HIGH IMPEDANCE
D7 MSB
DATA OUT
D6 D5 D4
Status Register Read (Opcode: 57H)
CS
SCK tSU
1
2
3
4
5
6
7
8
9
10
11
12
17
18
COMMAND OPCODE SI
0 1 0 1 0 1 1 1
tV SO HIGH IMPEDANCE
D7 MSB
STATUS REGISTER OUTPUT
D6 D5 D4 D0 LSB D7 MSB D6
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Detailed Bit-level Read Timing - SPI Mode 0
Continuous Array Read (Opcode: E8H)
CS
SCK tSU SI
1
2
62
63
64
65
66
67
1
1
X
X
X
tV SO HIGH IMPEDANCE
DATA OUT
D7 D6 D5 D2 D1
LSB D0
MSB D7 D6 D5
BIT 8447 OF PAGE n
BIT 0 OF PAGE n+1
Burst Array Read with Synchronous Delay (Opcode: E9H)
CS
SCK tSU SI
1
2
62
63
64
65
66
1
2
31
32
33
32 CLOCKS
0 1 X X X
tV SO HIGH IMPEDANCE
D7
DATA OUT
D6 D1
LSB D0 Don't Care D7
MSB D6
BIT 8447 OF PAGE n
BIT 0 OF PAGE n+1
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1638F-DFLSH-09/02
Detailed Bit-level Read Timing - SPI Mode 0 (Continued)
Main Memory Page Read (Opcode: D2H)
CS
SCK tSU
1
2
3
4
5
60
61
62
63
64
65
66
67
COMMAND OPCODE SI
1 1 0 1 0 X X X X X
tV SO HIGH IMPEDANCE
D7 MSB
DATA OUT
D6 D5 D4
Buffer Read (Opcode: D4H or D6H)
CS
SCK tSU
1
2
3
4
5
36
37
38
39
40
41
42
43
COMMAND OPCODE SI
1 1 0 1 0 X X X X X
tV SO HIGH IMPEDANCE
D7 MSB
DATA OUT
D6 D5 D4
Status Register Read (Opcode: D7H)
CS
SCK tSU
1
2
3
4
5
6
7
8
9
10
11
12
16
17
COMMAND OPCODE SI
1 1 0 1 0 1 1 1
tV SO HIGH IMPEDANCE
D7 MSB D6
STATUS REGISTER OUTPUT
D5 D4 D1 D0 LSB D7 MSB
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Detailed Bit-level Read Timing - SPI Mode 3
Continuous Array Read (Opcode: E8H)
CS
SCK tSU SI
1
2
63
64
65
66
67
0
1
X
X
X
tV SO HIGH IMPEDANCE
DATA OUT
D7 D6 D5 D2 D1
LSB D0
MSB D7 D6 D5
BIT 8447 OF PAGE n
BIT 0 OF PAGE n+1
Burst Array Read with Synchronous Delay (Opcode: E9H)
CS
SCK tSU SI
1
2
63
64
65
66
1
2
31
32
33
32 CLOCKS
0 1 X X X
tV SO HIGH IMPEDANCE
D7
DATA OUT
D6 D1
LSB D0 Don't Care
MSB D7 D6
BIT 8447 OF PAGE n
BIT 0 OF PAGE n+1
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1638F-DFLSH-09/02
Detailed Bit-level Read Timing - SPI Mode 3 (Continued)
Main Memory Page Read (Opcode: D2H)
CS
SCK tSU
1
2
3
4
5
61
62
63
64
65
66
67
68
COMMAND OPCODE SI
0 1 0 1 0 X X X X X
tV SO HIGH IMPEDANCE
D7 MSB
DATA OUT
D6 D5 D4
Buffer Read (Opcode: D4H or D6H)
CS
SCK tSU
1
2
3
4
5
37
38
39
40
41
42
43
44
COMMAND OPCODE SI
0 1 0 1 0 X X X X X
tV SO HIGH IMPEDANCE
D7 MSB
DATA OUT
D6 D5 D4
Status Register Read (Opcode: D7H)
CS
SCK tSU
1
2
3
4
5
6
7
8
9
10
11
12
17
18
COMMAND OPCODE SI
0 1 0 1 0 1 1 1
tV SO HIGH IMPEDANCE
D7 MSB
STATUS REGISTER OUTPUT
D6 D5 D4 D0 LSB D7 MSB D6
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Detailed Parallel Read Timing - SPI Mode 0
Continuous Array Read (Opcode: E8H)
CS
CLK tSU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
1
2
62
63
64
65
66
67
CMD
ADDR
X
X
X
tV HIGH IMPEDANCE
DATA OUT
DATA DATA DATA DATA DATA DATA DATA DATA DATA
BYTE 1055 OF PAGE n
BYTE 0 OF PAGE n+1
Burst Array Read with Synchronous Delay (Opcode: E9H)
CS
CLK tSU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
1
2
62
63
64
65
66
1
2
31
32
33
32 CLOCKS
CMD ADDR X X X
tV HIGH IMPEDANCE
DATA OUT
DATA DATA DATA DATA Don't Care DATA DATA
BYTE 1055 OF PAGE n
BYTE 0 OF PAGE n+1
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1638F-DFLSH-09/02
Detailed Parallel Timing - SPI Mode 0 (Continued)
Main Memory Page Read (Opcode: D2H)
CS
CLK tSU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
1
2
3
4
5
60
61
62
63
64
65
66
67
COMMAND OPCODE
CMD ADDR ADDR ADDR X X X X X X
tV HIGH IMPEDANCE
DATA OUT
DATA DATA DATA DATA
Buffer Read (Opcode: D4H or D6H)
CS
CLK tSU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
1
2
3
4
5
6
7
COMMAND OPCODE
CMD ADDR ADDR ADDR X
tV HIGH IMPEDANCE
DATA OUT
DATA DATA DATA MSB
Status Register Read (Opcode: D7H)
CS
CLK tSU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
1
2
3
4
CMD
tV HIGH IMPEDANCE
DATA DATA DATA
STATUS REGISTER OUTPUT
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Detailed Parallel Read Timing - SPI Mode 3
Continuous Array Read (Opcode: E8H)
CS
CLK tSU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
1
2
63
64
65
66
67
CMD ADDR
X
X
X
tV HIGH IMPEDANCE
DATA OUT
DATA DATA DATA DATA DATA DATA DATA DATA DATA
BYTE 1055 OF PAGE n
BYTE 0 OF PAGE n+1
Burst Array Read with Synchronous Delay (Opcode: E9H)
CS
CLK tSU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
1
2
63
64
65
66
1
2
31
32
33
32 CLOCKS
CMD ADDR X X X
tV HIGH IMPEDANCE
DATA OUT
DATA DATA DATA DATA DON'T CARE DATA DATA
BYTE 1055 OF PAGE n
BYTE 0 OF PAGE n+1
31
1638F-DFLSH-09/02
Detailed Parallel Read Timing - SPI Mode 3 (Continued)
Main Memory Page Read (Opcode: D2H)
CS
CLK tSU I/07-I/O0 (INPUT) I/07-I/O0 (OUTPUT)
1
2
3
4
5
61
62
63
64
65
66
67
68
COMMAND OPCODE
CMD ADDR ADDR ADDR X X X X X X
tV HIGH IMPEDANCE
DATA OUT
DATA DATA DATA DATA
Buffer Read (Opcode: D4H or D6H)
CS
CLK tSU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
1
2
3
4
5
6
7
8
9
CMD
ADDR ADDR ADDR
X
tV HIGH IMPEDANCE
DATA OUT
DATA DATA DATA DATA
Status Register Read (Opcode: D7H)
CS
CLK tSU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
1
2
3
4
CMD
tV HIGH IMPEDANCE
DATA DATA DATA
STATUS REGISTER OUTPUT
HIGH IMPEDANCE
32
AT45DB642
1638F-DFLSH-09/02
AT45DB642
Figure 1. Algorithm for Programming or Reprogramming of the Entire Array Sequentially
START provide address and data
BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H)
END
Notes:
1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-bypage. 2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array.
33
1638F-DFLSH-09/02
Figure 2. Algorithm for Randomly Modifying Data
START provide address of page to modify MAIN MEMORY PAGE TO BUFFER TRANSFER (53H, 55H) If planning to modify multiple bytes currently stored within a page of the Flash array
BUFFER WRITE (84H, 87H)
MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H)
BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H)
AUTO PAGE REWRITE (58H, 59H)
(2)
INCREMENT PAGE (2) ADDRESS POINTER
END
Notes:
1. To preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations. 2. A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command must use the address specified by the Page Address Pointer. 3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase/program operations have accumulated before rewriting all pages of the sector. See application note AN-4 ("Using Atmel's Serial DataFlash") for more details.
Sector Addressing
PA12 0 0 0 0 * * * 1 1 1 1 PA11 0 0 0 0 * * * 1 1 1 1 PA10 0 0 0 0 * * * 1 1 1 1 PA9 0 0 0 1 * * * 0 0 1 1 PA8 0 0 1 0 * * * 0 1 0 1 PA7 0 X X X * * * X X X X PA6 0 X X X * * * X X X X PA5 0 X X X * * * X X X X PA4 0 X X X * * * X X X X PA3 0 X X X * * * X X X X PA2 - PA0 X X X X * * * X X X X Sector 0 1 2 3 * * * 29 30 31 32
34
AT45DB642
1638F-DFLSH-09/02
AT45DB642
Ordering Information
fSCK (MHz) 20
(1)
ICC (mA) Active 10
(1)
Standby 0.01 0.01
Ordering Code AT45DB642-TC AT45DB642-TI
Package 40T 40T
Operation Range Commercial (0C to 70C) Industrial (-40C to 85C)
20(1) Note:
10(1) 1. Serial Interface
Package Type 40T 40-lead, Plastic Thin Small Outline Package (TSOP)
35
1638F-DFLSH-09/02
Packaging Information
40T - TSOP
PIN 1
0 ~ 8
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation CD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 19.80 18.30 9.90 0.50 NOM - - 1.00 20.00 18.40 10.00 0.60 0.25 BASIC 0.17 0.10 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 20.20 18.50 10.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40T, 40-lead (10 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 40T REV. B
R
36
AT45DB642
1638F-DFLSH-09/02
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e-mail
literature@atmel.com
Web Site
http://www.atmel.com
(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
Atmel(R) and DataFlash(R) are the registered trademarks of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
1638F-DFLSH-09/02 /xM

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